Intel had 84 patents in digitalization during Q1 2024. Intel Corp’s patents filed in Q1 2024 focus on efficient partitioning and construction of graphs for high-performance search applications, generating new data records based on hash values of chained data records, deriving calibration parameters for a cable modem transceiver, and authentication methods using hashing algorithms for device inspection. Additionally, there are systems and methods for a network proxy server to deliver video content efficiently to mobile devices using a multipath transport protocol. GlobalData’s report on Intel gives a 360-degree view of the company including its patenting strategy. Buy the report here.

Intel grant share with digitalization as a theme is 55% in Q1 2024. Grant share is based on the ratio of number of grants to total number of patents.

Recent Patents

Application: Method and system for efficient partitioning and construction of graphs for scalable high-performance search applications (Patent ID: US20240104136A1)

The patent filed by Intel Corp. describes methods, apparatus, and systems for efficiently partitioning and constructing graphs for scalable high-performance search applications. The method involves analyzing patterns of ternary keys with wildcards, storing keys with the same pattern in the same subset, and merging patterns when there are more than a target number of subgraphs. The patterns can be uncompressed or compressed, and merge costs are calculated based on quantum keys for merging candidate patterns with minimum cost. The method supports tables with hundreds of thousands or millions of entries and involves generating table entries corresponding to merged patterns and partitioning them into sub-tables associated with sub-graphs.

The patent also covers a non-transitory machine-readable medium with instructions for executing the partitioning method on computing apparatus, including creating compressed patterns, analyzing patterns, storing keys in subsets, and merging patterns. Additionally, the patent describes an apparatus with means for partitioning ternary keys by creating compressed patterns, analyzing patterns, storing keys in subsets, and merging patterns until the target number of subgraphs is reached. The apparatus can include processing elements, memory, and programmable logic components like FPGAs or ASICs, and can be used in infrastructure processing units, data processing units, or edge processing units for efficient graph construction and search applications.

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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.