IBM has patented a semiconductor device with a unique multi-layer bottom spacer design to reduce parasitic capacitance. The structure includes a fin, bottom source/drain structure, and epitaxial semiconductor layer. The layers of the spacer vary in height to optimize performance. GlobalData’s report on International Business Machines gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on International Business Machines, M2M communication interfaces was a key innovation area identified from patents. International Business Machines's grant share as of March 2024 was 75%. Grant share is based on the ratio of number of grants to total number of patents.
Semiconductor device with multi-layer bottom spacer for parasitic capacitance
A recently granted patent (Publication Number: US11973125B2) discloses a semiconductor device designed to address parasitic capacitance from the bottom source/drain structure. The device includes a fin, a bottom source/drain structure around the fin, and a multi-layer bottom spacer with three adjacently positioned layers. The layers are made of different dielectric materials, with the third layer having a stepped profile to reduce parasitic capacitance. Additionally, each layer of the bottom spacer has a specific vertical height above the bottom source/drain structure, with the layer farthest from the fin having a greater vertical height than the layer closest to the fin.
Furthermore, the semiconductor device features a layer of epitaxial semiconductor between the bottom source/drain structure and the second layer of the bottom spacer. This configuration helps optimize the device's performance by effectively managing parasitic capacitance. The design also ensures that the layers of the bottom spacer extend down to the underlying semiconductor substrate, providing structural stability and enhancing the overall functionality of the device. Overall, the patented semiconductor device offers a novel approach to mitigating parasitic capacitance in semiconductor devices, potentially leading to improved efficiency and performance in various electronic applications.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
