According to GlobalData’s company profile on Nordic Semiconductor, M2M communication interfaces was a key innovation area identified from patents. Nordic Semiconductor's grant share as of September 2023 was 30%. Grant share is based on the ratio of number of grants to total number of patents.

A processing apparatus with deferred-push processor registers

A recently filed patent (Publication Number: US20230315456A1) describes a processing apparatus with unique features. The apparatus includes a processor with multiple deferred-push processor registers and processor-register control circuitry. The control circuitry consists of status registers that correspond to each deferred-push register. When a new value is written to a deferred-push register, the control circuitry detects it and checks the status register for that register. If the status register indicates an unsaved status, the control circuitry reads the current value from the register before the write operation completes. It then writes the current value to memory and sets the status register to indicate a saved status.

The processing apparatus also includes memory to which the control circuitry can write the current value of the deferred-push register. Additionally, the processor has hardware interrupt inputs, and the control circuitry sets all status registers to the unsaved status when a hardware interrupt request is received. The apparatus has an interrupt vector table and software interrupt handlers stored in memory. When a hardware interrupt request is received, the processor performs a context switch and branches to the appropriate interrupt handler based on the interrupt vector table.

The processor has a stack pointer register and another processor register. It uses the stack pointer to determine the memory address to which it should push the value of the other register. The control circuitry includes a context stack pointer register, which helps determine the memory address to write the current value of the deferred-push register. In response to a hardware interrupt request, the processor can change the stack pointer by an amount that accommodates all deferred-push registers and the context stack pointer register.

The control circuitry is responsible for pushing various values, such as the program counter, status registers, and context stack pointer, to memory addresses determined by the stack pointer. It can also copy the value from the stack pointer register to the context stack pointer register. The control circuitry determines the address to push a deferred-push register value by applying a constant offset to the value in the context stack pointer register.

The processing apparatus supports context switches and delays pushing values stored in deferred-push registers to memory until the respective register is written to from within the new context. When returning from an interrupt handler routine, the control circuitry checks the status registers and reads the pushed values from memory if they hold the saved status.

The processing apparatus supports nested interrupts and tail-chained interrupt processing, where multiple interrupts are handled successively without returning to the interrupted process. It also avoids popping any pushed status register values when returning from a first interrupt handler if a second interrupt is pending.

Overall, this patent describes a processing apparatus with unique features that enhance interrupt handling and context switching capabilities.

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