NXP Semiconductors had 17 patents in big data during Q2 2024. The patents filed by NXP Semiconductors NV in Q2 2024 include a method for sharing a PCIe EP device in a PCIe cluster, a fault detection system for polynomial operations, an elliptic curve cryptography authentication method, shuffling and sliding subgroup techniques for data block manipulation, and a fault detection system for a digital signature algorithm. These patents cover a range of data processing and security technologies. GlobalData’s report on NXP Semiconductors gives a 360-degree view of the company including its patenting strategy. Buy the report here.
NXP Semiconductors had no grants in big data as a theme in Q2 2024.
Recent Patents
Application: Id-based transaction routing for pcie endpoint lending (Patent ID: US20240211425A1)
The patent filed by NXP Semiconductors NV describes a method, apparatus, and architecture for sharing a PCIe EP device with multiple lendee data processing systems in a PCIe cluster. The system involves extracting an RID value from a received PCIe transaction message, identifying an interconnect target port value corresponding to a lendee data processing system, and routing the message through an interconnect on the host data processing system to deliver it to the lendee data processing system. The method does not require address-based routing or customization of the lendee data processing system.
The claims detail a computer-implemented method for sharing a PCIe endpoint device, involving receiving a PCIe transaction message, extracting an RID value, identifying an interconnect target port value, and routing the message to the lendee data processing system. The method includes programming routing logic with configuration values, mapping RID values to interconnect target port values, and utilizing a lookup table for this mapping. The host data processing system is configured to route messages through the interconnect without address-based routing or customization of the lendee data processing system. The system is designed to efficiently share PCIe devices in a cluster without the need for complex address translation mechanisms.
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