Soitec has been granted a patent for a method to fabricate a growth substrate. The process involves creating a crystalline semiconductor surface layer with alternating InGaN and AlGaN layers, ensuring a different lattice parameter from the seed layer, followed by transferring and heat treating to form a relaxation structure. GlobalData’s report on Soitec gives a 360-degree view of the company including its patenting strategy. Buy the report here.
According to GlobalData’s company profile on Soitec, 3D memory devices was a key innovation area identified from patents. Soitec's grant share as of June 2024 was 52%. Grant share is based on the ratio of number of grants to total number of patents.
Method for fabricating a semiconductor growth substrate
The granted patent US12040424B2 outlines a method for fabricating a growth substrate, which involves several key steps. Initially, a donor substrate is prepared by forming a crystalline semiconductor surface layer on a seed layer of a carrier. This surface layer consists of alternating InGaN primary layers and AlGaN secondary layers, with specific indium and aluminum concentrations and thicknesses selected to ensure that a homogeneous AlInGaN layer has a different natural lattice parameter than the seed layer. The method further includes transferring a portion of this surface layer to a relaxation substrate, incorporating a creep layer to create a relaxation structure, defining growth islands within the surface layer, and heat treating the structure to partially relax these growth islands.
The claims detail specific parameters for the layers involved in the process. Each primary layer is defined to have an indium concentration between 0% and 50% and a thickness ranging from 10 to 150 nm, while the secondary layers have an aluminum concentration between 0% and 20% and a thickness of 2 to 15 nm. The method allows for 2 to 20 alternations of these layers, with the overall surface layer thickness exceeding 200 nm. Additional steps include heat treatment for homogenization and the transfer of growth islands to a final carrier, with a dielectric layer positioned between the growth islands and the carrier. This comprehensive approach aims to enhance the properties of the growth substrate for potential applications in semiconductor technology.
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