VIA Technologies has been granted a patent for a prefetching method in a microprocessor. The method involves issuing L3 prefetches for a memory block based on certain conditions, and then issuing L2 prefetches for cache lines corresponding to the L3 prefetches when reaching the end of the memory block. GlobalData’s report on VIA Technologies gives a 360-degree view of the company including its patenting strategy. Buy the report here.
According to GlobalData’s company profile on VIA Technologies, Device power optimization was a key innovation area identified from patents. VIA Technologies's grant share as of April 2024 was 83%. Grant share is based on the ratio of number of grants to total number of patents.
Prefetching method in microprocessor for cache line optimization
A recently granted patent (Publication Number: US11940921B2) discloses a novel microprocessor design featuring an L1 cache, L2 cache with a bounding box prefetch unit and L2 fill queue, and an L3 cache. The bounding box prefetch unit allocates entries in the L2 fill queue based on L2 cache misses and issues L3 prefetches for memory blocks under specific conditions. Additionally, L2 prefetches are issued for cache lines corresponding to L3 prefetches when the cache lines reach the end of the memory block.
Furthermore, the patent details a prefetching method implemented in the microprocessor, where entries in the L2 fill queue are allocated based on L2 cache misses. Subsequently, all remaining prefetches for a memory block are issued as L3 prefetches, with L2 prefetches for cache lines triggered upon reaching the end of the memory block. The method includes conditions such as a threshold quantity of set bits in an access bitmask and a minimum quantity of accesses, as well as suspending pattern matching based on these conditions and monitoring for pattern matches under specific criteria. The method also enables L2 and L3 prefetches based on bit settings in the L2 cache, enhancing overall performance and efficiency in data retrieval processes.
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