Will Semiconductor has been granted a patent for a method of forming a deep trench isolation structure for a CMOS image sensor. The method involves creating a trench in a semiconductor substrate, depositing a conformal layer of boron-doped dielectric in the trench, filling the recess in the trench with a second material, and annealing the conformal layer to drive boron into the substrate and form a passivation layer. The second material used is doped polysilicon, and the annealing process also electrically activates the doped polysilicon. GlobalData’s report on Will Semiconductor gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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Method for forming deep trench isolation structure for cmos image sensor
A recently granted patent (Publication Number: US11769779B2) describes a method for forming a deep trench isolation structure for a CMOS image sensor. The method involves several steps to create a structure that enhances the performance and functionality of the image sensor.
The method begins by forming a trench in a semiconductor substrate, extending from one side to the other. The trench has an opening on one side, and the bottom and sides are made of the semiconductor substrate. A conformal layer of boron (B)-doped dielectric is then deposited on the bottom and sides of the trench. This layer is less than half the width of the trench, leaving a recess in the trench.
Next, a second material, specifically doped polysilicon, is deposited on the conformal layer of B-doped dielectric in the trench. This material fills the recess in the trench, extending at least to the first side. The conformal layer of B-doped dielectric is then annealed, causing boron from the layer to be driven into the semiconductor substrate. This forms a B-doped region in the substrate, which acts as a passivation layer next to the conformal layer of B-doped dielectric. The annealing process also electrically activates the doped polysilicon.
The method includes specific details regarding the deposition processes and parameters. For example, the conformal layer of B-doped dielectric can be deposited using atomic layer deposition or chemical vapor deposition at a temperature between 300°C and 500°C. The doped polysilicon can be deposited by chemical vapor deposition at a temperature between 450°C and 550°C.
The patent also describes additional steps that can be performed after the annealing process. These steps involve forming a photodiode, thinning the semiconductor substrate, and forming an isolation well. Further steps include forming an interlayer dielectric layer, a buffer oxide layer, a metal grid, a color filter, and a microlens. The interlayer dielectric layer can be bonded to an application-specific integrated circuit (ASIC) wafer.
Overall, this patent presents a method for forming a deep trench isolation structure for a CMOS image sensor that involves precise deposition techniques and annealing processes. The resulting structure enhances the performance and functionality of the image sensor, potentially leading to improved image quality and sensitivity.