Cirrus Logic has been granted a patent for a chip scale package (CSP) design with two sets of contact balls, a semiconductor die, and a channel routing region devoid of contact balls. The CSP is designed for direct mounting and electrical coupling to a host device substrate. GlobalData’s report on Cirrus Logic gives a 360-degree view of the company including its patenting strategy. Buy the report here.

According to GlobalData’s company profile on Cirrus Logic, Voice biometrics was a key innovation area identified from patents. Cirrus Logic's grant share as of January 2024 was 64%. Grant share is based on the ratio of number of grants to total number of patents.

Chip scale package with specific contact ball arrangement

Source: United States Patent and Trademark Office (USPTO). Credit: Cirrus Logic Inc

A recently granted patent (Publication Number: US11887924B2) discloses a chip scale package (CSP) design that includes a semiconductor die, two sets of CSP contact balls or bumps positioned within the perimeter of the die, and a channel routing region devoid of any contact balls or bumps. The CSP is designed to be mounted directly on a substrate of a host device, with the contact balls or bumps facilitating electrical coupling. The unique feature of this CSP is the presence of a channel routing region created by a discontinuity in the arrangement of contact balls or bumps, allowing for efficient signal routing within the package.

Furthermore, the patent also covers a substrate arrangement designed to receive the CSP, comprising two sets of substrate contact pads and a channel routing region with signal routing channels in a metal layer of the substrate. The channel routing region facilitates the efficient transfer of signals between the CSP and the substrate, enhancing the overall performance of the electronic device. Additionally, the substrate includes a second metal layer connected to the first metal layer through vias, further optimizing signal transmission within the package. Overall, this patented CSP and substrate arrangement offer a novel and efficient solution for electronic devices requiring compact and high-performance packaging.

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GlobalData, the leading provider of industry intelligence, provided the underlying data, research, and analysis used to produce this article.

GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.