Jenoptik has patented a method for testing optoelectronic chips on a wafer, involving precise alignment of electrical and optical interfaces. The process includes adjusting the wafer in three steps to ensure optimal contact and alignment, enabling the routing of electrical and optical signals for testing. GlobalData’s report on Jenoptik gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Jenoptik, Lidar for weather forecasting was a key innovation area identified from patents. Jenoptik's grant share as of February 2024 was 48%. Grant share is based on the ratio of number of grants to total number of patents.
Method for testing optoelectronic chips on wafer with specific alignment
A recently granted patent (Publication Number: US11906579B2) discloses a method for testing optoelectronic chips on a wafer, involving a positioning table and a contacting module with electrical and optical interfaces. The method includes precise alignment of optical deflection elements with optical interfaces, followed by routing of electrical and optical signals through the interfaces associated with each other. The alignment process involves adjusting the positioning table in the X and Y directions to achieve maximum optical signal intensity, and subsequently deflecting the chips in the X-Y direction based on the coupling angle of the optical deflection element before final positioning in the Z direction.
Furthermore, the patent claims include additional features such as storing the offset resulting from the initial and subsequent adjustment positions for further chip adjustments, monitoring and correcting the optical working distance to maintain the predefined pressing force, and replacing needles in the contacting module when the optical working distance falls below a predetermined minimum distance. Additionally, the method involves ensuring that the optical signals over-radiate the interface when coupled and have a specific radiation intensity distribution when entering the interfaces. These claims highlight the comprehensive nature of the testing method, ensuring accurate alignment and signal routing for optoelectronic chips on a wafer, ultimately improving the efficiency and reliability of the testing process.
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