PDF Solutions. has filed a patent for a method to assign root causes for wafer defects. By comparing bin map data of current and prior wafers, the system determines the probability of the same root cause and labels the wafer accordingly. This innovation aims to streamline defect analysis in semiconductor manufacturing. GlobalData’s report on PDF Solutions gives a 360-degree view of the company including its patenting strategy. Buy the report here.

According to GlobalData’s company profile on PDF Solutions, CMOS gate array designing was a key innovation area identified from patents. PDF Solutions's grant share as of January 2024 was 63%. Grant share is based on the ratio of number of grants to total number of patents.

Root cause assignment for wafer defects based on bin map

Source: United States Patent and Trademark Office (USPTO). Credit: PDF Solutions Inc

The patent application (Publication Number: US20230377132A1) describes a method for analyzing defects in semiconductor wafers during production runs. The method involves receiving a wafer bin map with a defect, identifying the product flow used for the wafer, retrieving prior wafer bin maps from previous production runs with similar product flows, and analyzing the current defect by comparing it with the prior maps to assign a root cause. The analysis includes comparing patterns on the maps, clustering patterns, generating statistical distributions, and determining distances between wafers to associate root causes with defects.

Furthermore, the method includes steps for tuning boundary conditions, calculating statistics for spatial zones on the wafer map, and classifying defects based on statistical calculations. The patent also covers a computer-readable medium with instructions for executing the method, including comparing patterns, clustering, generating statistical distributions, and determining distances. Additionally, a computer-implemented method for a graphical user interface (GUI) for semiconductor processes is described, allowing users to view wafer bin maps, compare them with prior maps, assign root causes to defects, and provide user controls for further analysis and updates. Overall, the patent application aims to improve defect analysis in semiconductor production through a systematic and data-driven approach.

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