Synopsys. has been granted a patent for a level shifter circuit that converts a lower power clock signal into a higher power clock signal. The circuit includes an input clock buffer that processes both the original and the shifted clock signals, enhancing signal compatibility across different power levels. GlobalData’s report on Synopsys gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Synopsys, AI assisted CAD was a key innovation area identified from patents. Synopsys's grant share as of July 2024 was 74%. Grant share is based on the ratio of number of grants to total number of patents.
Level shifter circuit for clock signal power level conversion
The granted patent US12073876B2 describes a level shifter circuit designed to facilitate the conversion of clock signals between different power levels within integrated circuits. The circuit includes a level shifter that receives a first clock signal associated with a lower power level (VDDP) and generates a second clock signal linked to a higher power level (VDDA). The design features an input clock buffer with two inputs: one for the second clock signal from the level shifter and another for the first clock signal, allowing for parallel processing. The claims further specify that the first power level may correspond to a peripheral voltage, while the second power level is associated with a bitcell array voltage.
Additionally, the patent outlines a method for implementing this level-shifting process, which includes generating an output clock signal based on the voltage difference between the two power levels. This output clock signal can be utilized by a memory periphery and a memory timer, both connected in parallel to the input clock buffer. The design accommodates both single rail and dual rail configurations and allows for the coupling of the level shifter's input terminal to an input/output circuit. The patent also encompasses a non-transitory computer-readable medium containing instructions for generating a digital representation of the described level-shifting circuit, emphasizing its applicability in modern integrated circuit design.
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