Taiwan Semiconductor Manufacturing had two patents in big data during Q4 2023. The patent filed by Taiwan Semiconductor Manufacturing Co Ltd in Q4 2023 describes an in-memory computing circuit that includes a core die, conductive pillars, and memory dies. The memory dies are connected to the core die through the conductive pillars and are used to perform computing operations. One of the memory dies is located on the bottommost memory die and all memory dies receive input data from the core die through a common input terminal. GlobalData’s report on Taiwan Semiconductor Manufacturing gives a 360-degreee view of the company including its patenting strategy. Buy the report here.
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Taiwan Semiconductor Manufacturing grant share with big data as a theme is 50% in Q4 2023. Grant share is based on the ratio of number of grants to total number of patents.
Recent Patents
Application: In-memory computing circuit and fabrication method thereof (Patent ID: US20230361081A1)
The patent filed by Taiwan Semiconductor Manufacturing Co Ltd describes an in-memory computing circuit that includes a core die, conductive pillars, and memory dies for implementing computing operations. The memory dies are coupled to the core die through the conductive pillars, with input data transmitted from the core die to the memory dies through the conductive pillars. Each memory die stores weighting values and performs multiply-accumulate operations based on the input data and stored values. The core die manages communication of input and output data through the conductive pillars, with the memory dies vertically spaced apart and configured for pipeline computing operations.
The in-memory computing circuit also involves a method of manufacturing the circuit, which includes forming a core die with input and output terminals and coupling memory dies to the core die through conductive pillars. The memory dies store weighting values and perform parallel computing operations, with input data received from the core die and output data transmitted back through the core die's output terminals. The memory dies are vertically spaced apart, with at least one memory die disposed on the bottommost memory die. The circuit is designed for efficient and effective computing operations, particularly for neural network computing and convolution operations.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
