Tower Semiconductor has been granted a patent for a semiconductor structure that includes a group IV substrate with group IV dies separated by a scribe line. The structure also features group III-V chiplets and optoelectronic devices, allowing for improved functionality and monitoring capabilities. GlobalData’s report on Tower Semiconductor gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Tower Semiconductor, Solid state memory was a key innovation area identified from patents. Tower Semiconductor's grant share as of February 2024 was 85%. Grant share is based on the ratio of number of grants to total number of patents.
Semiconductor structure with group iv and iii-v devices
A recently granted patent (Publication Number: US11929442B2) discloses a semiconductor structure that includes a group IV substrate with group IV dies separated by scribe lines. The structure further comprises functional group IV devices within the group IV dies, a patterned group III-V device situated over the scribe line, and a functional group III-V optoelectronic device positioned at the edge of one of the group IV dies. The optoelectronic device is placed adjacent to the patterned group III-V device along the edge, with both devices aligned perpendicular to the edge. Additionally, the patent describes the configuration of multiple patterned group III-V devices over horizontal and vertical scribe lines, each being distinct from the other.
Moreover, the patent also details a method for producing the semiconductor structure, involving the placement of a group III-V chiplet over the group IV substrate and scribe line, followed by the patterning of the chiplet to create the patterned group III-V device. The method includes forming a functional group III-V optoelectronic device over one of the group IV dies, positioned at the edge and adjacent to the patterned group III-V device. The process also encompasses the production of additional patterned group III-V devices over different scribe lines, emphasizing the uniqueness of each device within the horizontal and vertical configurations. Overall, the patent highlights a novel semiconductor structure and method that integrate group IV and group III-V devices in a precise and efficient manner.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
