Advanced Micro Devices had 26 patents in future of work during Q1 2024. AMD’s patents in Q1 2024 focus on power management, clock signal generation, data processing array instruction generation, supply voltage regulation, and efficient routing of scan data in three-dimensional packaging. The patents cover technologies such as adaptive oscillators, common drain amplifiers, and voter circuits for improved performance and efficiency in computing systems. GlobalData’s report on Advanced Micro Devices gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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Advanced Micro Devices grant share with future of work as a theme is 50% in Q1 2024. Grant share is based on the ratio of number of grants to total number of patents.
Recent Patents
Application: Droop detection and control of digital frequency-locked loop (Patent ID: US20240106438A1)
The patent filed by Advanced Micro Devices Inc. describes an integrated circuit that includes a power supply monitor, a clock generator, and a divider. The power supply monitor triggers a signal when the power supply voltage drops below a certain threshold, prompting the clock generator to adjust the frequency of the clock signal over time based on a frequency control word. The divider then divides the frequency of the clock signal to provide a second clock signal in response to the trigger signal.
The integrated circuit also includes features such as a fast droop detector in the power supply monitor, a digital frequency locked loop in the clock generator, and the ability to adjust the clock signal frequency using a native adaptive stretch with programmable parameters. Additionally, the clock generator can provide the frequency control word based on various control mechanisms, adjusting it to the largest change indicated by these mechanisms. The method outlined in the patent involves determining the power supply voltage status, activating a trigger signal and dividing the clock signal if the voltage is below the threshold, and selectively stretching and unstretching the clock signal based on control mechanisms if the voltage is above the threshold, with provisions for hysteresis periods and resuming normal operations.
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