Camtek’s patent describes a method and system for classifying semiconductor wafer defects using deep learning. The approach integrates multiple imaging modalities and reference images to enhance classification accuracy while reducing the need for extensive labeled data and training time through a Directed Acyclic Graph architecture of machine learning models. GlobalData’s report on Camtek gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Camtek, Pose estimation was a key innovation area identified from patents. Camtek's grant share as of July 2024 was 37%. Grant share is based on the ratio of number of grants to total number of patents.
Method for classifying semiconductor wafer defects using deep learning
The patent US12020417B2 outlines a method and system for classifying defects in semiconductor wafers using advanced imaging and machine learning techniques. The method involves utilizing multiple imaging units with different modalities to capture images of semiconductor wafers. A computing unit is employed, which includes a processor, database, and memory, to manage two or more machine learning (ML) models. These models are trained on a diverse set of labeled images to classify defects present on semiconductor dies. The architecture of the ML models is organized in a Directed Acyclic Graph (DAG), which facilitates a structured approach to defect classification, allowing for the potential skipping of certain models based on prior outputs. This process culminates in a classification decision generated through post-processing that incorporates the results from the active models.
The claims further specify that the imaging modalities can include X-ray, grayscale, and color imaging, among others. The ML models can be categorized as supervised, semi-supervised, or unsupervised, with a focus on deep learning techniques. The training process leverages historical images to create a robust dataset for model training. Additionally, the system is designed to utilize metrology information, such as defect size, to enhance classification accuracy. The architecture allows for different paths within the DAG, enabling the classification of multiple defects with varying levels of model engagement, thereby optimizing the classification process based on the complexity of the defects being analyzed. This innovative approach aims to improve the efficiency and accuracy of defect detection in semiconductor manufacturing.
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