According to GlobalData’s company profile on Accton Technology, V2V communication antennas was a key innovation area identified from patents. Accton Technology's grant share as of June 2023 was 1%. Grant share is based on the ratio of number of grants to total number of patents.

Patent granted for network device sending synchronization packets

A recently granted patent (Publication Number: US11664967B2) describes a network device designed for sending synchronization packets to a slave device. The synchronization packets contain a timestamp field and a correction field. The network device includes a counting circuit that provides a calendar time TOD, a communication chip with two ports and a timestamp circuit, and a processor connected to the communication chip's first port.

The processor is configured to obtain a remainder R by performing a MOD function computation or a division computation on the calendar time TOD and a bit number N. The processor then writes the calendar time TOD and the remainder R into the synchronization packet. In another embodiment, the processor computes the difference between a first remainder R1 and the calendar time TOD and writes this difference into the timestamp field, while writing 0 or a null value into the correction field.

When the communication chip receives a delay request packet, the network device records the delay request packet input time TiREQ. The counting circuit provides a delay request packet receiving calendar time TODREQ. The processor obtains a corresponding quotient QREQ and a corresponding remainder RREQ based on the delay request packet receiving calendar time TODREQ and the bit number N. It then generates a delay response packet using the quotient QREQ, the bit number N, and the delay request packet input time TiREQ. If the delay request packet input time TiREQ is larger than the corresponding remainder RREQ, the processor adds 1 to the quotient QREQ.

In another aspect of the invention, the network device obtains a first calendar time TOD1, a first remainder R1, and a first chip receiving time Ti1 in a first period when a first synchronization packet is generated. It also obtains a second calendar time TOD2 and a second chip receiving time Ti2 in a second period when a second synchronization packet is generated. The processor writes the second calendar time TOD2, the first remainder R1, and the first chip receiving time Ti1 into the second synchronization packet. It can also compute a second remainder R2 based on the second calendar time TOD2 and the bit number N and write it into the second synchronization packet.

Overall, this patent describes a network device that efficiently generates synchronization packets with accurate timestamps and correction fields, allowing for precise synchronization with slave devices. It also includes features for handling delay request packets and generating appropriate delay response packets.

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