Cadence Design Systems has been granted a patent for a charge model that can be used in electronic design automation (EDA) for timing analysis of circuit designs. The charge model can predict the charge at an input of a cell instance for different input voltage waveforms and mitigate the time delay impact caused by the Miller effect. The patent involves generating equations based on waveform data and input capacitance data, and fitting a charge model by determining parameter values. This charge model can be used in timing analysis of circuit designs that include the cell instance. GlobalData’s report on Cadence Design Systems gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Cadence Design Systems, manufacturability analysis was a key innovation area identified from patents. Cadence Design Systems's grant share as of September 2023 was 86%. Grant share is based on the ratio of number of grants to total number of patents.
Charge model for delay calculation of a circuit design
A recently granted patent (Publication Number: US11775719B1) describes a computer-readable medium that contains instructions for a device to perform various operations related to generating and using a charge model for a circuit design. The device receives a selection of a cell instance and accesses waveform data and input capacitance data for the input of the cell instance. Based on this data, the device generates a set of equations and determines a set of values for the parameters of these equations, resulting in a fitted charge model for the input. The set of values for the parameters is then stored for use in performing timing analysis of the circuit design.
The patent also mentions that the device can perform timing analysis of the circuit design by using the stored set of values for the parameters with a charge prediction equation to calculate a timing delay. The cell instance can be an inverter or a buffer, and the waveform data can be accessed from library data for the cell instance. Similarly, the input capacitance data can be accessed from cell library data for the cell instance.
The waveform data describes multiple waveforms for the input corresponding to different slews at the input, and the input capacitance data describes capacitance values at the input as a function of voltage level, slew, or load at the output of the cell instance. The formulation of the charge model is based on a discretized formulation of the input charge at the input, which is determined by static input capacitance, input voltage, back-Miller capacitance, and output voltage.
The determination of the set of values for the parameters of the equations can be done using least squares to approximately solve the equations. In some cases, a sub-plurality of equations can be used instead of the full set of equations. The patent also describes a device that includes a memory storing the instructions and a hardware processor to perform the operations described above. Additionally, a method is outlined that involves accessing waveform data and input capacitance data, generating equations, determining values for the parameters, and using the parameters to calculate a timing delay using a charge prediction equation.
Overall, this patent presents a computer-readable medium, device, and method for generating and using a charge model for timing analysis of a circuit design. The approach involves accessing waveform and input capacitance data, generating equations, determining parameter values, and using these values to calculate timing delays.
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