Cadence Design Systems has patented a processor load-store unit that executes load/store instructions in parallel using separate pipelines and tag memory arrays. The unit resolves tag write conflicts and utilizes a data cache tag replay scheme to enhance performance. The apparatus includes control circuitry for efficient instruction replay. GlobalData’s report on Cadence Design Systems gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Cadence Design Systems, Manufacturability analysis was a key innovation area identified from patents. Cadence Design Systems's grant share as of May 2024 was 51%. Grant share is based on the ratio of number of grants to total number of patents.
Processor load-store unit with parallel pipelines and tag memory arrays
A recently granted patent (Publication Number: US11983538B2) discloses an apparatus comprising a processor, cache circuitry, and a load-store unit designed to execute multiple types of memory access instructions using parallel pipelines. The load-store unit includes control circuitry to manage tag memory arrays for each pipeline, ensuring matching tag information is stored. In case of arbitration loss, the control circuitry replays instructions of the losing pipeline, including the oldest dependent instruction and all younger instructions, maintaining efficient memory access operations.
Furthermore, the patent details a method implemented by the load-store unit, where memory access instructions are executed in parallel pipelines with cache hit determination using separate tag memory arrays. The control circuitry arbitrates between pipelines to prevent conflicts when writing to tag memory arrays in a given cycle. This method ensures optimal performance by replaying instructions of the losing pipeline, including the oldest dependent instruction and all younger instructions, enhancing the efficiency of memory access operations in the processor. The patent also covers a non-transitory computer-readable storage medium containing design information for a hardware integrated circuit, specifying the inclusion of the load-store unit with arbitration capabilities and replay functionality for efficient memory access management.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
