According to GlobalData’s company profile on Rambus, M2M communication interfaces was a key innovation area identified from patents. Rambus's grant share as of September 2023 was 69%. Grant share is based on the ratio of number of grants to total number of patents.

Memory device with error detection and correction capabilities

A recently granted patent (Publication Number: US11775369B2) describes a memory device embodied as an integrated circuit. The memory device includes at least one memory array, interface circuitry, array control circuitry, and command error detection circuitry.

The interface circuitry receives write commands, associated data, error detection information, and error correction codes from a memory controller. The array control circuitry is responsible for detecting and correcting errors in the associated data using the error correction codes and writing the data into the memory array. Additionally, the command error detection circuitry detects errors in the write commands based on the provided information and prevents the writing of data associated with erroneous commands into the memory array.

The memory device utilizes dynamic random access memory (DRAM) cells in each array of the memory array. It also includes circuitry to communicate information about the existence of errors in the write commands to the memory controller. This communication is done unsolicitedly through a separate link not used for data exchange.

The information used for error detection is parity information, and the error correction code employed is a cyclic code. In cases where the associated data is transferred over a serial communication link, the memory device includes a deserializer to deserialize the data and correct any errors in the deserialized data before writing it into the memory array.

The memory device further includes a buffer to queue write commands for a predetermined period of time. If no errors are detected in the write commands during this time, the array control circuitry writes the associated data into the memory array for the queued write commands. The array control circuitry also services data from the buffer when fulfilling a read command directed to data in the buffer.

The patent also describes the structure of the write commands, which consist of first fields and second fields. The information provided only identifies the existence of errors in the first fields and does not allow for their correction.

In summary, the granted patent discloses a memory device that utilizes error correction codes and error detection circuitry to ensure the accuracy of data written into memory arrays. It includes features such as communication of error information to the memory controller, serialization and deserialization of data, and a buffer for queuing write commands. The memory device is particularly suited for use with DRAM arrays and can prevent the writing of data associated with erroneous commands.

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