Texas Instruments has been granted a patent for methods and systems to facilitate atomic compare and swap in cache for a coherent level 1 data cache system. The patent describes a circuit device comprising cache memories and a cache controller that can determine the presence of data in the cache memory and request data from another cache memory if necessary. GlobalData’s report on Texas Instruments gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Texas Instruments, Under-screen biometric identification was a key innovation area identified from patents. Texas Instruments's grant share as of September 2023 was 67%. Grant share is based on the ratio of number of grants to total number of patents.
Cache system for atomic compare and swap operations
A recently granted patent (Publication Number: US11775446B2) describes a circuit device that includes a cache hierarchy and a cache controller. The circuit device comprises a first cache memory that stores a set of data and a state memory that stores the state of each unit of data in the first set. The cache controller is connected to the first cache memory and the state memory and can also connect to a second cache memory associated with the cache hierarchy.
The cache controller is configured to receive a compare-and-swap operation that specifies a memory address. Based on this operation, the cache controller determines whether a second set of data associated with the memory address is stored in the first cache memory. If the second set of data is not present in the first cache memory, the cache controller requests the second set of data from the second cache memory. However, if the second set of data is present in the first cache memory, the cache controller determines the state associated with it using the state memory. If the state is a shared state, the cache controller requests the second set of data from the second cache memory.
The patent also describes additional features of the circuit device. For example, if the second set of data is present in the first cache memory and the state associated with it is a modified state or an exclusive state, the cache controller can use the first set of data stored in the first cache memory to perform the compare-and-swap operation. The cache controller can also set the state associated with the second set of data in the state memory to an exclusive state based on either providing the request to the second cache memory or receiving the second set of data from the second cache memory.
The circuit device includes a processor coupled to the cache controller, and a tag random access memory is also connected to the cache controller to determine whether the second set of data associated with the memory address is stored in the first cache memory.
Overall, this patent describes a circuit device with a cache hierarchy and a cache controller that efficiently manages data storage and retrieval based on compare-and-swap operations. The circuit device can determine the presence of data in the cache memory, its state, and request data from the second cache memory as needed. This technology can potentially improve the performance and efficiency of cache systems in various computing applications.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
