According to GlobalData’s company profile on Winbond Electronics, Magnetic RAMs was a key innovation area identified from patents. Winbond Electronics's grant share as of September 2023 was 77%. Grant share is based on the ratio of number of grants to total number of patents.

Manufacturing method for a semiconductor structure

A recently filed patent (Publication Number: US20230317520A1) describes a manufacturing method for a semiconductor structure. The method involves several steps to form active areas, dielectric layers, and contact holes. The method also includes the formation of a gate structure on one of the active areas. The patent claims that the method improves the efficiency and performance of semiconductor structures.

In more detail, the method begins by forming first active areas that define a cell region, as well as a second and third active area that define a peripheral region. A first dielectric layer is then formed on these active areas. A patterned region is created in the first dielectric layer, consisting of a cavity region surrounding a dielectric region corresponding to the second active area. A filling layer is then added to the cavity region, followed by a cap layer and a second dielectric layer.

Next, first contact holes and at least one second contact hole are formed, penetrating the layers mentioned above. The first contact holes expose a portion of the first active areas, while the second contact hole replaces the dielectric region and exposes a portion of the second active area. Metal layers are then filled into these contact holes.

The method also includes the formation of a gate structure on the third active area. Another patterned region is formed in the first dielectric layer, with a dielectric region corresponding to the gate structure. Before filling the cavity region, a first barrier layer is formed, and before adding the metal layers, a second barrier layer is formed in the contact holes.

The resulting semiconductor structure consists of first active areas defining a cell region, a second and third active area defining a peripheral region, and various dielectric and metal layers. The metal layers are electrically connected to the active areas and the second active area. The structure may also include a gate structure on the third active area.

Overall, this patent describes a manufacturing method and resulting semiconductor structure that aim to improve the efficiency and performance of semiconductor devices. The method involves precise formation of active areas, dielectric layers, and contact holes, as well as the addition of barrier layers and metal layers. The resulting structure provides electrical connections and improved functionality.

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