Keysight Technologies has been granted a patent for a method involving programmable data plane processors for traffic impairment. The method includes configuring a packet processing pipeline using command and control instructions received via an API, and applying impairments to test packets for testing a system under test. The impairments can be applied based on per-flow selection techniques or random selection techniques. GlobalData’s report on Keysight Technologies gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Keysight Technologies, Network traffic analysis was a key innovation area identified from patents. Keysight Technologies's grant share as of September 2023 was 78%. Grant share is based on the ratio of number of grants to total number of patents.
Method for programmable data plane processor based traffic impairment
A recently granted patent (Publication Number: US11765068B2) describes a method and system for programmable data plane processor based traffic impairment. The method involves using a first impairment device with a programmable data plane processor to receive command and control instructions via an application programming interface (API) from a test controller. These instructions are used to configure a packet processing pipeline implemented using the programmable data plane processor. The packet processing pipeline is then used to apply one or more impairments to test packets for testing a system under test (SUT).
The impairments applied by the programmable data plane processor can be based on a per-flow selection technique utilizing switching rules in switching tables or a random or pseudo-random selection technique utilizing random number generators and/or probability density functions. The first impairment device can be cross-connected to an emulation device for providing an emulated data center switching fabric. The SUT can be directly connected to the emulation device or the first impairment device.
The command and control instructions can include data plane processing logic written in P4, network programming language (NPL), or other programming languages. The first impairment device can be connected to a second impairment device for causing additional impairments or a spool of cable for adding delay or latency.
The system described in the patent includes at least one programmable data plane processor and a first impairment device with the programmable data plane processor. The system operates similarly to the method, receiving command and control instructions via an API from a test controller to configure a packet processing pipeline implemented using the programmable data plane processor. The packet processing pipeline is then used to apply impairments to test packets for testing a SUT.
The patent claims various impairments that can be applied, including frame or packet drop, duplication, reordering, burst, delay increase, jitter increase, latency increase, frame error, header field scrambling, traffic shaping, bandwidth limiting, policy-based behavior causing impairment, packet misdirection or misrouting, link failure, link flap, or checksum or validation error.
Overall, this patent describes a method and system for programmable data plane processor based traffic impairment, allowing for the testing of systems under various impairments using a configurable packet processing pipeline.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
