Micron Technology has been granted a patent for semiconductor dies with protected edges. The method involves forming trenches on the front side of a substrate, with each trench corresponding to a scribe line. A composite layer, including a metallic layer for electromagnetic interference shielding, is formed on the sidewalls of the trenches. The substrate is then thinned from the back side to separate individual semiconductor dies. The resulting semiconductor die includes integrated circuitry at the front side, a dielectric layer at the back side, and a metallic layer completely covering the outermost sidewall. GlobalData’s report on Micron Technology gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Micron Technology, 3D memory devices was a key innovation area identified from patents. Micron Technology's grant share as of September 2023 was 68%. Grant share is based on the ratio of number of grants to total number of patents.
A patent granted for protecting edges of semiconductor dies
A recently granted patent (Publication Number: US11776908B2) describes a semiconductor die with specific features and a semiconductor die assembly using these dies. The semiconductor die includes integrated circuitry on the front side and a dielectric layer on the back side. The outermost sidewall of the die is completely covered by a metallic layer, which extends from the front side to the back side. This metallic layer acts as a protective barrier for the die.
In addition to the metallic layer, the semiconductor die may also include a diffusion barrier between the outermost sidewall and the metallic layer. This diffusion barrier prevents metallic constituents of the metallic layer from interfering with the die's functionality. The diffusion barrier can be made of materials such as silicon nitride, tantalum, or tantalum nitride. The metallic layer itself is typically made of copper.
The semiconductor die may also have one or more vias that extend from the front side to the back side. These vias provide electrical connections for the integrated circuitry on the back side of the die.
The patent also describes a semiconductor die assembly that includes a stack of these semiconductor dies. Each die in the stack has a composite layer surrounding its outermost sidewall, consisting of a diffusion barrier and a metallic layer. The diffusion barrier is in direct contact with the outermost sidewall, while the metallic layer is in direct contact with the diffusion barrier. The metallic layers of adjacent dies in the stack may be separated by a gap or connected to each other.
The topmost die in the stack may have a second metallic layer that is parallel to the interface die, which can be a logic die or an interposer die. The other dies in the stack are memory dies.
To protect the stack of semiconductor dies, an encapsulant surrounds the entire assembly, extending from the interface die to the topmost semiconductor die.
Overall, this patent presents a semiconductor die and a semiconductor die assembly with specific features that enhance the performance and protection of the dies. These innovations can potentially improve the reliability and functionality of semiconductor devices in various applications.
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GlobalData, the leading provider of industry intelligence, provided the underlying data, research, and analysis used to produce this article.
GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
