Rambus has been granted a patent for a memory device with a memory controller that enables the application of different impedance values for on-die termination (ODT) to various inputs. The controller sends command/address signals and chip select signals to the memory device, along with register values for impedance selection. GlobalData’s report on Rambus gives a 360-degree view of the company including its patenting strategy. Buy the report here.
According to GlobalData’s company profile on Rambus, M2M communication interfaces was a key innovation area identified from patents. Rambus's grant share as of May 2024 was 39%. Grant share is based on the ratio of number of grants to total number of patents.
Memory device with adjustable impedance values for ca and cs

A newly granted patent (Publication Number: US12002540B2) discloses a memory controller designed to efficiently control the operation of a memory device. The memory controller includes a command/address (CA) transmission circuit responsible for sending CA signals and chip select signals to the memory device. Additionally, the memory controller sends register values to the memory device for storage in multiple registers, allowing for the selection of impedance values for on-die termination (ODT) impedances applied to various inputs of the memory device. These register values enable the selective application of ODT impedances to specific inputs receiving CA signals, as well as the chip select input.
Furthermore, the memory controller dynamically controls termination of individual signal lines of the CA bus, enhancing the overall efficiency of the memory device. The controller also includes a driver for the chip select signal and multiple registers within the memory device to store values for enabling different ODT impedance values for various inputs. The patent also covers a method of operation for the memory controller, detailing the process of sending CA signals and register values to the memory device to facilitate the selection and application of ODT impedances. Overall, the patent highlights an innovative memory controller system that optimizes memory device performance through the precise control of impedance values and signal termination processes.
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