SiFive has filed a patent for systems and methods that provide memory protection for vector operations. The patent describes a method that involves partitioning a vector into subvectors of different lengths, checking for memory protection violations, and accessing the elements of the subvectors accordingly. The patent also includes an integrated circuit with a processor core, memory protection circuit, and vector partition circuit. GlobalData’s report on SiFive gives a 360-degree view of the company including its patenting strategy. Buy the report here.
According to GlobalData’s company profile on SiFive, vector processing optimization was a key innovation area identified from patents. SiFive's grant share as of September 2023 was 25%. Grant share is based on the ratio of number of grants to total number of patents.
Memory protection for vector operations

A recently filed patent (Publication Number: US20230315649A1) describes an integrated circuit designed to execute instructions efficiently. The circuit includes a processor core with a pipeline that can execute constant-stride vector memory instructions. It also features a memory protection circuit that checks for memory protection violations using a protection granule. Additionally, the circuit includes a vector partition circuit that performs several functions.
The vector partition circuit determines the maximum length of a vector, which corresponds to the number of vector elements that can be accessed in a single clock cycle. This maximum length is determined based on the protection granule and the stride of the vector identified by a vector memory instruction. The circuit then partitions the vector into a subvector of the maximum length and one or more additional subvectors with lengths less than or equal to the maximum length.
Before checking for memory protection violations, the circuit accesses the elements of the subvector. It then uses the memory protection circuit to check whether accessing elements of the additional subvectors will cause a memory protection violation.
The memory protection circuit can check either two addresses or a single address per clock cycle, depending on its configuration. In the case of checking two addresses, the vector partition circuit inputs the address of the first element and the address of the last element of the subvector during a single clock cycle. If the memory protection circuit detects a memory protection violation associated with an element of one of the additional subvectors, the circuit raises an exception.
The maximum length of the vector is directly proportional to the protection granule and inversely proportional to the stride. It is also a power of two. The vector can be a unit-stride vector with a stride of one.
Overall, this integrated circuit aims to optimize the execution of instructions, particularly constant-stride vector memory instructions, by efficiently partitioning vectors and checking for memory protection violations. It provides a solution for improving performance and ensuring memory protection in integrated circuits.
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