STMicroelectronics has been granted a patent for a method to reset a master device in a system on a chip. The method involves monitoring the state of transactions initiated by the master device and resetting it when the transactions are completed or when a reset command is received. The patent also includes provisions for resetting the master device if the transactions are not completed within a maximum response time. GlobalData’s report on STMicroelectronics gives a 360-degree view of the company including its patenting strategy. Buy the report here.

According to GlobalData’s company profile on STMicroelectronics, Quantum dot devices was a key innovation area identified from patents. STMicroelectronics's grant share as of September 2023 was 67%. Grant share is based on the ratio of number of grants to total number of patents.

Method for resetting a master device on a system on a chip

Source: United States Patent and Trademark Office (USPTO). Credit: STMicroelectronics NV

A recently granted patent (Publication Number: US11775037B2) describes a method and system for managing transactions in a system on a chip (SoC) device. The method involves monitoring the state of outstanding transactions initiated by a master circuit on a bus. When the transactions are determined to be in a completed state, the master circuit is reset after receiving a reset command. A transaction is considered completed when the master circuit receives a response to the request. On the other hand, if the outstanding transactions are in a non-completed state after the expiration of the maximum response time, the master circuit is reset after receiving the reset command. A non-completed state indicates that the master circuit failed to receive a response to the request.

The system on the chip device includes an interface with an input port and an output port. The monitoring of the outstanding transactions involves detecting signals over these ports. A transaction is defined as the emission of a request on the output port and the reception of a response on the input port. The monitoring process also includes counting the number of requests emitted and the number of responses received. If the number of responses received is equal to the number of requests emitted, it indicates that the transaction is in a completed state.

The method further includes generating a blocking signal in response to the reset command and blocking the initiation of new transactions by the master circuit. This is achieved by activating a reset signal and deactivating it during the reset process. Additionally, the method involves blocking the reception of response signals from the bus to the master circuit by erasing the response signal on the bus.

The system on the chip device also includes a reset management circuit that is responsible for monitoring the state of outstanding transactions and resetting the master circuit. The reset management circuit communicates with the master circuit and the bus. It generates a blocking signal upon receiving the reset command and blocks the initiation of new transactions by the master circuit. The reset management circuit can also communicate the response signal to the master circuit when the bus is in a forced busy state.

Overall, this patent presents a method and system for effectively managing transactions in a system on a chip device, ensuring that completed transactions are properly reset and non-completed transactions are handled appropriately.

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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.