Taiwan Semiconductor Manufacturing has been granted a patent for a method of generating a layout diagram for wire routing in a multi-patterning context. The method involves placing a cut pattern over a conductive pattern, determining if it violates a design rule, and temporarily preventing placement until a correction is made. The patent aims to improve the efficiency and accuracy of wire routing arrangements. GlobalData’s report on Taiwan Semiconductor Manufacturing gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Taiwan Semiconductor Manufacturing, 3D memory devices was a key innovation area identified from patents. Taiwan Semiconductor Manufacturing's grant share as of September 2023 was 69%. Grant share is based on the ratio of number of grants to total number of patents.
Method for generating layout diagram of wire routing arrangement
A recently granted patent (Publication Number: US11775727B2) describes a method for generating a layout diagram of a wire routing arrangement in a multi-patterning context with multiple masks. The method involves placing a given cut pattern at a candidate location over a corresponding portion of a conductive pattern in a metallization layer. The method then determines whether the candidate location violates a design rule by resulting in a non-circular group or a cyclic group. If a violation is detected, the placement of the cut pattern is temporarily prevented until a correction is made to avoid violating the design rule.
The method includes various scenarios for making corrections to
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