Cadence Design Systems has patented a method for packing transaction layer packets at a link layer, involving generating channel type data, identifying slot formats, selecting a format based on message types, and packing packets into a slot. This innovation aims to optimize data transmission efficiency in protocol stacks. GlobalData’s report on Cadence Design Systems gives a 360-degree view of the company including its patenting strategy. Buy the report here.

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According to GlobalData’s company profile on Cadence Design Systems, Manufacturability analysis was a key innovation area identified from patents. Cadence Design Systems's grant share as of January 2024 was 86%. Grant share is based on the ratio of number of grants to total number of patents.

Efficient packing of tl packets in link layer protocol stack

Source: United States Patent and Trademark Office (USPTO). Credit: Cadence Design Systems Inc

A recently granted patent (Publication Number: US11886372B1) discloses a channel arbitration method that involves generating channel type data to identify the type of message channel for a first transaction layer (TL) packet, selecting slot formats for packing TL packets based on the channel type data, determining the availability of a second TL packet for packing, and packing both TL packets into a single link layer packet. The method aims to efficiently pack TL packets into slots based on message types and channel priorities, ultimately enhancing data transmission across a link to a receiving device. The patent also describes a system comprising a processor and a protocol stack that implements the channel arbitration method to generate and transmit TL packets across a lane of a link to a receiving device, showcasing the practical application of the patented method in a system environment.

Furthermore, the patent details the protocol stack's ability to evaluate message channel information, identify slot formats based on TL packet types, and select slot formats for packing TL packets during flit generation. The system's channel arbitrator, including a channel scheduler and a slot format identifier, plays a crucial role in determining slot packing data and generating single link layer packets with packed TL packets. By incorporating priority requests and channel priority data, the system ensures efficient data transmission by selecting slot formats based on message types and channel priorities. The patent also highlights the versatility of the channel type data, which can identify various cache channel types such as cache request, cache response, or cache data channel types, providing a comprehensive approach to channel arbitration in data transmission systems.

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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.