Hon Hai Precision Industry has been granted a patent for a semiconductor featuring 3D flash memory cells. The design includes a stack structure with multiple layers, including control and floating gate layers, a blocking layer, and a tunnel dielectric layer, enhancing data reading and writing efficiency through reduced channel resistance. GlobalData’s report on Hon Hai Precision Industry gives a 360-degree view of the company including its patenting strategy. Buy the report here.

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According to GlobalData’s company profile on Hon Hai Precision Industry, Device power optimization was a key innovation area identified from patents. Hon Hai Precision Industry's grant share as of June 2024 was 59%. Grant share is based on the ratio of number of grants to total number of patents.

3d flash memory semiconductor with improved data conduction

Source: United States Patent and Trademark Office (USPTO). Credit: Hon Hai Precision Industry Co Ltd

The granted patent US12046648B2 describes a semiconductor device featuring a unique configuration of storing cells designed to enhance data reading and writing processes. Each storing cell is constructed with a stack structure that includes multiple layers: at least one control gate layer, dielectric layers, and an erasing layer. The design incorporates a blocking layer that is coplanar with the control gate layer, a floating gate layer insulated from the control gate by the blocking layer, and a tunnel dielectric layer that envelops the sides of both the blocking and floating gate layers. Additionally, a channel layer is positioned adjacent to the tunnel dielectric layer. The semiconductor's operational efficiency is improved by applying a voltage to the erasing layer, which reduces the series resistance of the channel layer, facilitating quicker conduction during data operations.

The claims further specify the structural arrangement of the dielectric layers within the storing cells. A first thickness layer of the dielectric is situated between the erasing layer and the channel layer, oriented parallel to the surface of the stack structure, while a second thickness layer is positioned between the erasing layer and the floating gate layer, oriented perpendicularly. Notably, the breakdown voltage of the first thickness layer exceeds that of the second thickness layer, indicating a deliberate design choice aimed at optimizing the performance and reliability of the semiconductor device. This innovative configuration may provide advancements in semiconductor technology, particularly in enhancing the speed and efficiency of data processing.

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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.