Kudelski has been granted a patent for a chip design featuring a substrate with an integrated circuit, electrical contacts, and a security mechanism. This mechanism detects alterations in a conductive track, triggering countermeasures to disable the chip’s functionalities, enhancing its operational integrity and security. GlobalData’s report on Kudelski gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Kudelski, Digital watermarking was a key innovation area identified from patents. Kudelski's grant share as of July 2024 was 53%. Grant share is based on the ratio of number of grants to total number of patents.
Security mechanism for integrated circuit chip operation
The patent US12033925B2 describes a chip designed to enhance security through a specialized substrate configuration. The chip features a substrate with a first and second surface, where an integrated circuit is mounted on a designated landing zone on the first surface. Surrounding this landing zone is a peripheral region that houses multiple electrical contacts and wire-bonds connecting the integrated circuit to these contacts. The second surface includes solder ball connections, which are linked to the electrical contacts via internal connections in the substrate. A key aspect of the design is the inclusion of at least one conductive track routed through the landing zone, which is essential for the integrated circuit's operation. This track is integral to a security mechanism that detects any alterations, triggering countermeasures to disable or reset the chip's functionalities if tampering is detected.
Additionally, the patent outlines a method for protecting a wire-bond packaged ball grid array chip from unauthorized alterations. This method involves forming a substrate with a landing zone for the integrated circuit and establishing connections between the integrated circuit and peripheral contacts. The process includes routing a security track through the landing zone, which is electrically connected to solder balls positioned centrally beneath the landing zone. The security mechanism is designed to monitor the integrity of the security track, sending signals to detect any alterations. If an interference is detected, the mechanism can initiate countermeasures to reset or disable the chip's functions. The method also allows for the incorporation of ground and power planes within the substrate, further enhancing the chip's security features.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
