Power Integrations has been granted a patent for a method of forming contact regions in a high-voltage field effect transistor (HFET). The method involves providing a semiconductor material with active layers and a gate dielectric, forming contacts and passivation layers, and depositing interconnects and plugs. The patent also includes a claim for a high-voltage FET with specific features such as alternating plug locations and orthogonally offset plugs. GlobalData’s report on Power Integrations gives a 360-degree view of the company including its patenting strategy. Buy the report here.
According to GlobalData’s company profile on Power Integrations, Quantum dot devices was a key innovation area identified from patents. Power Integrations's grant share as of September 2023 was 65%. Grant share is based on the ratio of number of grants to total number of patents.
The patent is granted for a method of forming contact regions in a high-voltage field effect transistor

A recently granted patent (Publication Number: US11776815B2) describes a high-voltage field effect transistor (FET) with specific design features. The FET includes a first active layer made of a semiconductor material with a first bandgap and a second active layer made of a semiconductor material with a second bandgap. A gate dielectric is positioned near the second active layer, which is sandwiched between the first active layer and the gate dielectric.
The FET also features multiple contact regions, each with a contact that can supply or withdraw charge from the FET. A passivation layer is located near the contact and the gate dielectric, with part of the contact positioned between the passivation layer and the second active layer. An interconnect extends through the passivation layer and is connected to the contact at a via footprint region. The interconnect includes a first portion that is placed on the passivation layer, with the passivation layer separating it from the second active layer. A plurality of plugs is coupled to the first portion of the interconnect.
One notable aspect of the design is that the location of the plurality of plugs alternates along the same contact footprint from one contact region to another. In the vertical direction, the location of the plugs is orthogonally offset from their corresponding via footprint region. Additionally, the patent describes the use of a wing structure in the first portion of the interconnect, which is positioned off the center axis of the interconnect.
The patent also mentions the presence of an interlayer dielectric near the interconnect, with the first portion of the interconnect located between the interlayer dielectric and the passivation layer. The plurality of plugs extends into the interlayer dielectric, and each plug has a width, length, and height. The length of each plug is larger than its width, and the height is equal to or greater than the thickness of the interlayer dielectric.
Overall, this patent describes a high-voltage FET with specific design features related to the arrangement of contact regions, interconnects, and plugs. These features aim to improve the performance and efficiency of high-voltage FETs in various applications.
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