Qualcomm had 36 patents in robotics during Q2 2024. Qualcomm Inc’s patents filed in Q2 2024 focus on innovative technologies such as integrated circuits with directly coupled metal lines for reduced resistance, hybrid circuit boards combining functionality without exceeding height limits, routing raw debug data using trace infrastructure, integrated bare die packages with vertically-integrated components, and efficient processing of multiple non-overlapping layer images in display processing units. These patents showcase Qualcomm’s commitment to advancing semiconductor and communication technologies. GlobalData’s report on Qualcomm gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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Qualcomm had no grants in robotics as a theme in Q2 2024.
Recent Patents
Application: Integrated circuits (ICs) employing directly coupled metal lines between vertically-adjacent interconnect layers for reduced coupling resistance, and related methods (Patent ID: US20240203866A1)
The patent filed by Qualcomm Inc. describes integrated circuits (ICs) that utilize directly coupled metal lines between vertically-adjacent interconnect layers to reduce coupling resistance. This innovation eliminates the need for an intermediate vertical interconnect access layer with vias, resulting in reduced contact resistance between metal lines and a lower overall height of the IC. The use of insulating layers in select recessed regions between overlying and underlying interconnect layers helps to prevent unintended electrical coupling between intersecting metal lines.
The claims detail the structure and fabrication methods of the IC, including the arrangement of metal lines in different horizontal directions, the use of insulating layers to prevent electrical coupling, and the presence of power distribution networks and front-end-of-line structures. The method of fabricating the IC involves forming underlying and overlying interconnect layers, insulating layers, and metal lines in specific directions. The fabrication process also includes polishing, patterning, and etching steps to create the desired structure. Additionally, the method involves grinding down the substrate, recessing the substrate, and disposing dielectric layers to further enhance the structure of the IC.
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