Rambus. has been granted a patent for a hybrid memory system that combines fast, durable DRAM with slower, wear-sensitive flash memory. The system features an address buffer that maintains an SRAM cache for efficient data management between volatile and nonvolatile memory spaces. GlobalData’s report on Rambus gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Rambus, M2M communication interfaces was a key innovation area identified from patents. Rambus's grant share as of July 2024 was 68%. Grant share is based on the ratio of number of grants to total number of patents.
Hybrid memory system combining dram and flash memory
The granted patent US12072802B2 outlines a novel memory architecture that integrates both nonvolatile and volatile address spaces to enhance data storage and retrieval efficiency. The nonvolatile address space is designed to store data at specific nonvolatile-memory addresses, while the volatile address space serves as a cache for this data, utilizing first address tags that correspond to the nonvolatile addresses. Additionally, the memory system includes a cache that stores second address tags related to the data cached in the volatile address space. The architecture allows for the volatile address space to be organized into sets, each capable of storing blocks of data, which can be adjusted in number, thereby providing flexibility in memory management.
Further features of the memory system include the division of the volatile address space into cache lines, each containing storage for address tags and status indicators such as dirty and valid bits. The cache employs static random-access memory for storing second address tags and incorporates address logic to handle multiple access requests efficiently. The design also includes mechanisms for aggregating dirty cache lines into a write-back space and reordering cache lines to prioritize access to requested data. Overall, the patent presents a comprehensive approach to memory architecture that aims to optimize data caching and retrieval processes, addressing potential inefficiencies in traditional memory systems.
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