Synopsys has been granted a patent for a method that involves creating fin structures on a silicon substrate and reducing their width using a self-limiting fin etch process. Each iteration of the process decreases the width by one atomic layer, preventing fin collapse and current leakage. GlobalData’s report on Synopsys gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Synopsys, AI assisted CAD was a key innovation area identified from patents. Synopsys's grant share as of September 2023 was 75%. Grant share is based on the ratio of number of grants to total number of patents.
Method for creating fin structures with controlled width
A recently granted patent (Publication Number: US11776816B2) describes a method for creating fin structures on a silicon substrate with improved width control. The method involves applying a self-limiting fin etch process to decrease the width of the fin structures by only one atomic layer per iteration. This precise control prevents fin collapse and current leakage in the structures.
The self-limiting fin etch process consists of two steps: a self-limiting absorption process and a self-limiting removal process. In the absorption process, a chemical is used that only binds to the outermost atomic layer of the fin structures. This selective binding ensures that only the desired layer is affected. The removal process then removes the outermost atomic layer without disturbing the layer underneath.
The patent also mentions the creation of gate structures that wrap around the fin structures. This configuration is commonly used in Fin Field Effect Transistor (FinFET) devices and Gate All Around (GAA) devices, both of which benefit from the precise width control provided by the method.
Additionally, the patent describes a method for creating three-dimensional devices using the same self-limiting fin etch process. This method involves forming a fin hardmask pattern on the silicon substrate, using a fin etch process to create the fin structures, and then applying the self-limiting fin etch process to decrease their width.
Overall, this patent presents a novel method for creating fin structures on a silicon substrate with improved width control. The self-limiting fin etch process allows for precise adjustments to the width of the structures, preventing issues such as fin collapse and current leakage. This method has potential applications in the development of FinFET and GAA devices, as well as other three-dimensional devices.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
