Everspin Technologies. has filed a patent for a method of managing memory devices, involving error correction and mapping addresses. The method includes identifying mapped addresses, correcting errors, and updating the map table. The patent claims have been canceled. GlobalData’s report on Everspin Technologies gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Everspin Technologies, In-memory computing was a key innovation area identified from patents. Everspin Technologies's grant share as of January 2024 was 67%. Grant share is based on the ratio of number of grants to total number of patents.
Memory device management method with error correction and mapping
A recently filed patent (Publication Number: US20240006011A1) describes a memory device with a unique two-layer error correction code (ECC) system. The memory array in this device includes a two-layer ECC, where the second layer corrects errors detected after one or more first-layer ECC words. This two-layer ECC is specifically designed as a two-layer orthogonal ECC, enhancing error correction capabilities. Additionally, the memory device is equipped to manage memory operations efficiently. It can determine address mappings in a map table, identify and correct bit failures in ECC words, and update the map table accordingly. The device also includes a built-in self-repair (BISR) map table, BISR control logic circuitry, and a temperature sensor to monitor and adjust BISR functions based on temperature readings.
Furthermore, the patent outlines methods for managing the memory device effectively. These methods involve powering up the device, reading and checking bits for ECC failures, and responding accordingly to ensure smooth operation. In case of ECC failures, the device can perform various actions based on the severity of the error, such as writing back data to repair addresses, updating bit mappings, and notifying users of unrecoverable ECC failures. The methods also include fail-safe procedures like part recovery, resetting registers and configuration bits, and transitioning the device to a recovered state. Additionally, the patent introduces a method for handling write commands in memory banks, detecting ECC failures, and utilizing a threshold error detection (TED) table to generate new repair rows and update the BISR map table. These methods are designed to enhance memory management and error correction capabilities in the memory device.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
