Global Foundries had one patents in internet of things during Q4 2023. The patent filed by Global Foundries Inc in Q4 2023 describes a structure and method for integrating devices such as diodes for electrostatic discharge protection on RFIC chips. The structure includes a substrate with monocrystalline lower and upper portions separated by a high resistance portion, with isolation regions and device sections positioned above the high resistance portion. This design allows for improved ESD protection, larger RF voltage sustainability, area savings, reduced parasitic capacitance, and improved harmonics. GlobalData’s report on Global Foundries gives a 360-degreee view of the company including its patenting strategy. Buy the report here.
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Global Foundries grant share with internet of things as a theme is 0% in Q4 2023. Grant share is based on the ratio of number of grants to total number of patents.
Recent Patents
Application: Diode on high resistance portion of bulk semiconductor substrate and method (Patent ID: US20230402447A1)
The patent filed by Global Foundries Inc. discloses a structure and method for creating a semiconductor device with improved electrostatic discharge (ESD) protection on RFIC chips. The structure includes a substrate with monocrystalline lower and upper portions separated by a high resistance portion, such as a trap-rich amorphous layer. The device section of the upper portion is positioned laterally adjacent to an isolation region above the high resistance portion, where one or more diodes are located. These diodes are separated from the lower portion by the high resistance portion and can withstand larger RF voltages, reduce parasitic capacitance, and improve harmonics, providing area savings.
The claims of the patent detail the specific structure of the semiconductor device, including the configuration of the diodes, trap-rich layer, isolation regions, and silicide layers. The method outlined in the patent involves processing the semiconductor substrate to create the high resistance portion between the lower and upper portions, followed by forming the diodes adjacent to the upper surface. The method also includes forming isolation regions and device sections within the upper portion, where the diodes can be located. By utilizing trap-rich layers and specific semiconductor configurations, the disclosed structure and method aim to enhance ESD protection on RFIC chips while optimizing performance and efficiency.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
