HP has been granted a patent for a fluid ejection device with an integrated circuit that includes memory cells, address decoder, activation logic, and configuration logic. The configuration register enables or disables access to memory cells, enhancing the device’s functionality. GlobalData’s report on HP gives a 360-degree view of the company including its patenting strategy. Buy the report here.
According to GlobalData’s company profile on HP, Device power optimization was a key innovation area identified from patents. HP's grant share as of March 2024 was 58%. Grant share is based on the ratio of number of grants to total number of patents.
Integrated circuit for accessing memory in fluid ejection device

A recently granted patent (Publication Number: US11969995B2) discloses an integrated circuit designed to access a memory associated with a fluid ejection device. The integrated circuit comprises a plurality of memory cells, an address decoder to select memory cells based on an address, activation logic to activate selected memory cells using data and fire signals, and configuration logic to enable or disable access to the memory cells. Additionally, the configuration logic includes a configuration register to store data for enabling or disabling access and specifying write or read access to the memory cells. The integrated circuit also features a single interface connected to a host print apparatus and a write circuit for data writing to the memory cells.
Furthermore, the patent details the activation logic of the integrated circuit, which includes a first logic gate and a set of second logic gates. The first logic gate processes data and fire signals, while the second logic gates control the activation of memory cells based on inputs from the address decoder. Each memory cell in the plurality comprises non-volatile memory cells, and the integrated circuit is designed to interface with fluid actuation devices. The patent emphasizes the intricate design of the integrated circuit, highlighting the specific pathways and logic gates involved in controlling access to the memory cells and fluid actuation devices, ensuring efficient operation within a fluid ejection device.
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