Lattice Semiconductor has patented a system for failure characterization of secure programmable logic devices (PLDs). The system includes a secure PLD with programmable logic blocks and a configuration engine to program the PLD fabric. The PLD can receive a failure characterization command, erase portions of memory, and boot a debug configuration to identify operational failures. GlobalData’s report on Lattice Semiconductor gives a 360-degree view of the company including its patenting strategy. Buy the report here.
Access deeper industry intelligence
Experience unmatched clarity with a single platform that combines unique data, AI, and human expertise.
According to GlobalData’s company profile on Lattice Semiconductor, HDMI video transmission was a key innovation area identified from patents. Lattice Semiconductor's grant share as of May 2024 was 59%. Grant share is based on the ratio of number of grants to total number of patents.
Secure pld failure characterization system
A recently granted patent (Publication Number: US11971992B2) discloses a secure programmable logic device (PLD) failure characterization system. The system includes a secure PLD with programmable logic blocks arranged in a PLD fabric and a configuration engine to program the PLD fabric based on a configuration image stored in non-volatile memory (NVM). The secure PLD can receive a failure characterization command, erase customer data associated with the configuration image, load a debug configuration, and perform a debug process to identify failures in the PLD's operation. The system also involves authenticating commands using application keys and comparing trace IDs stored in the NVM.
Furthermore, the system allows for erasing or nullifying NVM sectors in a prioritized order, receiving debug configurations, generating debug digests, and re-provisioning the secure PLD after the debug process. An external system can provide debug configurations, receive debug digests, determine updated manufacturer trims based on the digests, and program the secure PLD with protected configurations. The secure PLD failure characterization system aims to enhance security and reliability by enabling secure debugging processes and re-provisioning mechanisms while safeguarding customer data and configurations. The system's methodical approach to failure characterization and debugging ensures the integrity and functionality of the secure PLD throughout its operational lifecycle.
To know more about GlobalData’s detailed insights on Lattice Semiconductor, buy the report here.
Data Insights
From
The gold standard of business intelligence.
Blending expert knowledge with cutting-edge technology, GlobalData’s unrivalled proprietary data will enable you to decode what’s happening in your market. You can make better informed decisions and gain a future-proof advantage over your competitors.

