Renesas Electronics has been granted a patent for a semiconductor memory device featuring a matrix of memory cells, word lines, and a row address decoder. The device operates in both normal and test modes, utilizing switch transistors to control conduction states and facilitate collective burn-in testing of memory cells. GlobalData’s report on Renesas Electronics gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Renesas Electronics, Under-screen biometric identification was a key innovation area identified from patents. Renesas Electronics's grant share as of July 2024 was 62%. Grant share is based on the ratio of number of grants to total number of patents.
Semiconductor memory device with test mode functionality
The patent US12073900B2 describes a semiconductor memory device designed to operate in both normal and test modes. The device features a matrix of memory cells connected to word lines, with a row address decoder that generates decode signals to control word line drivers. Key components include a first switch transistor, which is a P-channel MOS transistor, and multiple second switch transistors, which are N-channel MOS transistors. The first switch transistor's conduction state is modulated based on the operational mode, while the second switch transistors are controlled accordingly. The device is structured to facilitate collective burn-in testing of memory cells during the test mode, with specific configurations for the first and second switch transistors to manage power supply and reference potentials effectively.
Additionally, the patent outlines various configurations for auxiliary circuits that enhance the functionality of the word line drivers. These circuits can adjust the potential at different points along the word lines, ensuring proper voltage levels during both normal operation and testing phases. The test method described involves lowering the potential of the word lines to a reference level, activating decode signals for the memory cells, and subsequently raising the potential back to the power supply level. This method allows for comprehensive testing of the memory cells, including writing identical data to all cells prior to testing. The semiconductor memory device is identified as a Static Random Access Memory (SRAM), emphasizing its application in high-speed data storage solutions.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
