VIA Technologies has patented a microprocessor system that enhances branch prediction accuracy by quickly updating a quick predictor with information from a branch target address cache (BTAC). The BTAC overrides the quick predictor’s prediction if different, improving performance by utilizing global pattern history. GlobalData’s report on VIA Technologies gives a 360-degree view of the company including its patenting strategy. Buy the report here.
According to GlobalData’s company profile on VIA Technologies, Device power optimization was a key innovation area identified from patents. VIA Technologies's grant share as of May 2024 was 81%. Grant share is based on the ratio of number of grants to total number of patents.
Branch prediction system for microprocessors with quick predictor override

A recently granted patent (Publication Number: US11995447B2) discloses a novel microprocessor design featuring an instruction cache, a quick predictor, and a branch target address cache (BTAC). The quick predictor is responsible for generating branch predictions based on information associated with branch instructions, while the BTAC determines a second branch prediction by comparing this information. The BTAC can override the quick predictor's prediction based on the difference between the two predictions and update the quick predictor accordingly. This innovative design allows for efficient branch prediction updates within a microprocessor, enhancing overall performance.
Furthermore, the microprocessor described in the patent includes specific configurations for the quick predictor and BTAC, such as set-associative organizations and different branch prediction penalties. The quick predictor utilizes a local pattern history for biasing branch prediction direction, while the BTAC can provide cache instruction fetch re-directs based on updated predictions. The method outlined in the patent involves receiving information associated with branch instructions, generating branch predictions, comparing them, and updating the quick predictor accordingly. By optimizing the branch prediction process and utilizing both local and global pattern histories, this microprocessor design aims to improve overall efficiency and performance in processing instructions.
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