Synopsys has been granted a patent for a method involving computing time delays and commonality scores for paths in a circuit design. The method generates a graphical representation based on these scores to visually represent critical paths in a circuit design through a graphical user interface. GlobalData’s report on Synopsys gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Synopsys, AI assisted CAD was a key innovation area identified from patents. Synopsys's grant share as of April 2024 was 75%. Grant share is based on the ratio of number of grants to total number of patents.
Method for graphical representation of circuit paths based on scores
A recently granted patent (Publication Number: US11966677B1) discloses a method for analyzing circuit designs using a graphical representation. The method involves computing time delays for different paths in the circuit design, determining commonality and criticality scores based on the paths, and generating a graphical representation where the dimensions correspond to these scores. The graphical representation is then provided in a graphical user interface (GUI) to visually represent the paths in the circuit design. The method also includes features such as displaying severity, endpoints, and time per width for sub-paths, as well as generating different views based on stored records in a database during emulation of the circuit design.
Furthermore, the patent also describes a system and a computer-readable device that perform similar operations for analyzing circuit designs. The system includes memory for storing operations and processors for computing time delays, commonality scores, criticality scores, and generating graphical representations based on stored records. The system provides a GUI to represent the paths in the circuit design and allows users to interact with different views such as global timing view, hardware view, tabular path view, schematic path view, and source code view. Users can perform actions on selected portions of the views, such as expanding or collapsing sections, and the views are synchronized to provide a comprehensive analysis of various aspects of the circuit design. Additionally, the computer-readable device contains instructions for executing the operations related to computing time delays, commonality scores, criticality scores, and generating graphical representations for circuit design analysis.
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GlobalData, the leading provider of industry intelligence, provided the underlying data, research, and analysis used to produce this article.
GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
