AMD has filed a patent for methods to reduce warpage in stacked wafers. The process involves adding a warpage compensating layer, stacking wafers, connecting circuitry, and removing the compensating layer before dicing. This innovation aims to improve the reliability and performance of semiconductor devices. GlobalData’s report on Advanced Micro Devices gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Advanced Micro Devices, Device power optimization was a key innovation area identified from patents. Advanced Micro Devices's grant share as of January 2024 was 69%. Grant share is based on the ratio of number of grants to total number of patents.
Mitigating warpage on stacked wafers during wafer processing
A patent application (Publication Number: US20240038556A1) describes a method for mitigating warpage on stacked wafers in the semiconductor industry. The method involves depositing warpage compensating layers on the backside of wafers before stacking them to form a wafer stack. These compensating layers, which can be dielectric films or exposed metal films, help reduce warpage during the stacking process. The layers are removed from the wafers before dicing the wafer stack to form integrated circuit devices. Additional steps include stacking multiple wafers with interconnected circuitry, thinning wafers, and adding more layers to the stack to enhance the overall structure.
Furthermore, the method includes stacking wafers with interconnected circuitry, depositing dielectric warpage compensating layers on the backside of wafers, thinning the wafers, and removing the compensating layers before dicing the wafer stack. This approach aims to address warpage issues commonly encountered in the semiconductor industry during the wafer stacking process. By strategically applying these warpage compensating layers and following a precise sequence of steps, the method seeks to improve the overall quality and reliability of stacked integrated circuit devices. The patent application outlines various scenarios and configurations for implementing this method, highlighting the importance of mitigating warpage to ensure the performance and longevity of semiconductor devices.
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