Cambricon Technologies has filed a patent for an integrated circuit apparatus that performs neural network computing. The apparatus includes a processing apparatus, compiler, linker, and computing apparatus, which work together to implement the neural network computing. The patent also includes a storage apparatus for data storage. GlobalData’s report on Cambricon Technologies gives a 360-degree view of the company including its patenting strategy. Buy the report here.

According to GlobalData’s company profile on Cambricon Technologies, User journey analytics was a key innovation area identified from patents. Cambricon Technologies's grant share as of September 2023 was 20%. Grant share is based on the ratio of number of grants to total number of patents.

An integrated circuit apparatus for neural network computing

Source: United States Patent and Trademark Office (USPTO). Credit: Cambricon Technologies Corp Ltd

A recently filed patent (Publication Number: US20230274158A1) describes an integrated circuit apparatus for performing neural network computing. The apparatus includes a processing apparatus, a compiler, a linker, and a computing apparatus.

The processing apparatus is responsible for creating a template fuse unit, which is then converted into an object code by the compiler. The object code is then linked with a library to form an executable file. Finally, the computing apparatus performs the executable file to implement the neural network computing.

In the creation of the template fuse unit, the processing apparatus follows a fusion policy. It selects a starting layer according to a starting rule and performs a fusion based on the starting layer and check rules of the fusion policy.

During the conversion of the template fuse unit into the object code, the compiler derives the shape of the template fuse unit. It performs a reverse derivation forward from outputs for required input data and redundancy.

Additionally, the compiler derives the address of on-chip storage space of a whole control flow graph and implements access to a general address. It divides basic blocks initially according to a division of the template fuse unit and confirms the basic blocks and mutual relations between them after iterative operations.

The compiler also judges how much data in a previous template fuse unit can be used by a next template fuse unit and plans the address of on-chip storage space accordingly. The processing apparatus then allocates on-chip storage space based on the address of on-chip storage space.

The patent also mentions a board card that includes the integrated circuit apparatus described above. The board card consists of the processing apparatus, compiler, linker, and computing apparatus. The processing apparatus on the board card follows the same fusion policy to create the template fuse unit.

In summary, the patent describes an integrated circuit apparatus and a board card for performing neural network computing. The apparatus includes a processing apparatus, compiler, linker, and computing apparatus. The processing apparatus creates a template fuse unit, which is converted into an object code by the compiler. The object code is then linked with a library to form an executable file, which is performed by the computing apparatus to implement the neural network computing. The patent also describes various techniques used by the compiler to derive the shape of the template fuse unit and allocate on-chip storage space.

To know more about GlobalData’s detailed insights on Cambricon Technologies, buy the report here.

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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.