IBM and Siemens have entered a research collaboration aimed at advancing nanostack, the chip maker’s three-dimensional transistor architecture capable of packing nearly 100 billion transistors onto a fingernail-sized chip.
The partnership brings together IBM’s semiconductor device research and Siemens’ capabilities in electronic design automation (EDA), process simulation, lithography optimisation, and advanced manufacturing software. Their joint objective is to compress development timelines and build the manufacturing groundwork required to move nanostack toward commercial production.
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Described by IBM as the industry’s first known 3D nanosheet-based transistor design, nanostack vertically stacks and staggers transistors to achieve far greater density than conventional planar approaches. At its current 7 angstrom node, the architecture achieves nearly two times the transistor density per unit area compared with the nanosheet technology behind IBM’s 2nm chips, which were introduced in 2021.
The approach marks a departure from more than 60 years of semiconductor scaling that operated exclusively along the X and Y axes. By building upward on a given chip footprint, nanostack unlocks the Z axis for density gains.
IBM has drawn an analogy with high-density urban construction, where vertical building on a fixed plot yields significantly more usable space.
Engineers can also use different material combinations within each vertically stacked layer, making it possible to tune performance and power consumption for individual transistors without affecting others in the stack. IBM has said these capabilities deliver substantial gains in energy efficiency, overall performance, and SRAM scaling.
IBM silicon technology research and development (R&D) vice president Huiming Bu said: “Nanostack is a scalable transistor platform designed to shift device scaling from 2D to 3D, representing a new paradigm for the semiconductor industry and a path forward for the logic scaling needed to support AI and other emerging technologies over the coming decade.”
Although IBM demonstrated the viability of the architecture earlier this year, significant further development is needed before it can be manufactured at scale.
The collaboration will centre on creating advanced virtual models of nanostack devices, enabling the two companies to simulate performance, refine designs, and identify potential fabrication obstacles before physical chips are produced.
Work will also target the design, simulation, and lithography techniques required for future nanostack generations beyond the 7 angstrom node.
Siemens EDA IC portfolio executive vice president Ankur Gupta said: “Scaling semiconductors into the angstrom era demands tightly coupled co-optimisation between device physics, EDA design and manufacturing software, and manufacturing. As physical AI places extraordinary demands on silicon architecture, IBM’s 3D nanostack design represents a pivotal leap forward.”
IBM first disclosed the 7 angstrom breakthrough in June 2026, marking the company’s entry into sub-nanometre chip fabrication.
