Synopsys has announced the certification of its AI-powered electronic design automation (EDA) flows for Intel 14A process technology through an expanded collaboration with Intel Foundry.
The announcement was made at the 2026 DAC Chips to Systems Conference, reflecting ongoing efforts by both companies to advance design enablement from design technology co-optimisation through to system-aware co-design. The new certification builds on Synopsys’ previously validated EDA flows and intellectual property (IP) for Intel 18A and Intel 18A-P technologies.
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The collaboration aims to address challenges presented by angstrom-scale geometries in semiconductor manufacturing. Backside power delivery and dense 3D integration increase the complexity of electrical, thermal, and mechanical interactions.
Synopsys senior vice president Michael Buehler-Garcia said: “Angstrom-scale design is no longer only about extracting more power, performance, and area from a process node. It is about turning process innovation into predictable system-level outcomes.
“Together with Intel Foundry, Synopsys is helping customers accelerate convergence, reduce late-stage rework, and achieve first-pass silicon success.”
According to Synopsys, its certified, AI-enabled implementation and signoff flows, alongside multiphysics analysis solutions, have been integrated for use on the Intel 14A platform. These tools are designed for concurrent analysis of power integrity, thermal, and electromagnetic performance.
As multi-die design becomes more common in AI and high-performance computing (HPC) applications, Synopsys and Intel Foundry are broadening their partnership to support system-level integration and optimisation for advanced chiplet-based architectures.
The Synopsys reference design flow, based on its 3DIC Compiler, now supports Intel’s Embedded Multi-die Interconnect Bridge (EMIB) and EMIB-T packaging technologies.
The platform offers early bump and through-silicon via (TSV) planning, automated Universal Chiplet Interconnect Express (UCIe) and high bandwidth memory (HBM) routing, and unified multiphysics analysis across multiple dies and interconnects. This approach allows designers to identify and resolve power, thermal, and signal integrity issues during the design phase rather than post-production.
Intel senior vice president and foundry services general manager Shawn Han said: “In this increasingly AI-driven world, Intel Foundry is committed to supporting our customers by accelerating innovation and providing predictable execution from silicon to packaging on our most advanced technologies.
“Our wide-ranging collaboration with Synopsys, including AI-driven, certified flows and IP, gives our customers greater ease of use and confidence to achieve their design goals.”
To support ecosystem development, Synopsys is extending its portfolio of interface and foundation IP to include Intel 14A technologies, in addition to existing support for Intel 18A and 18A-P.
Expanded offerings for Intel 14A include interface IP such as 224G SerDes, PCIe 7.0, USB 4, and eUSB, as well as embedded memories, logic libraries, and I/O solutions.
Synopsys stated that these features are intended to address the throughput and connectivity requirements of emerging AI and HPC workloads while helping to manage performance, power consumption, and design costs.
Separately, Synopsys has introduced new autonomous agentic AI workflows for chip design, developed with Microsoft and available for evaluation on the Microsoft Discovery platform. These workflows include a fully autonomous AI-powered verification and root cause analysis (RCA) process, designed to expedite debug cycles and improve silicon quality.
Synopsys reported that initial evaluations indicate reductions of 25–40% in debug cycle times, with the potential to save weeks of engineering effort and increase productivity.
Additionally, an autonomous implementation and closure workflow leverages Synopsys’ implementation agents and Fusion Compiler on Microsoft Azure, with initial results reportedly showing improved quality-of-results.
