Tower Semiconductor has been granted a patent for a semiconductor structure that integrates a group IV substrate with a patterned group III-V device. The invention includes a dielectric layer with contact holes and a method for bonding and patterning the devices, facilitating optical and electrical connections. GlobalData’s report on Tower Semiconductor gives a 360-degree view of the company including its patenting strategy. Buy the report here.

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According to GlobalData’s company profile on Tower Semiconductor, Solid state memory was a key innovation area identified from patents. Tower Semiconductor's grant share as of June 2024 was 82%. Grant share is based on the ratio of number of grants to total number of patents.

Semiconductor structure with group iv and iii-v devices

Source: United States Patent and Trademark Office (USPTO). Credit: Tower Semiconductor Ltd

The patent US12009437B2 outlines a method for integrating group III-V chiplets with group IV substrates, which includes a group IV device. The process begins with bonding a group III-V chiplet to the group IV substrate, followed by patterning the chiplet to create a patterned group III-V device. A blanket dielectric layer is then formed over this device, and contact holes are created to access both the patterned group III-V device and the group IV device. A liner stack is formed within these contact holes, establishing direct contact with both devices, and a filler metal is deposited to complete the connection.

The claims further specify the materials and configurations involved in the process. For instance, the liner stack may include metal liners such as titanium, titanium nitride, tantalum, or nickel, with tungsten being a potential filler metal. The patterned group III-V device can be a photodiode featuring an N-type cathode made of indium phosphide and a P-type anode made of indium gallium arsenide. Additionally, the method allows for the planarization of the dielectric layer and ensures both optical and electrical connections between the patterned group III-V device and the group IV device within the substrate.

To know more about GlobalData’s detailed insights on Tower Semiconductor, buy the report here.

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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.