Cambricon Technologies has been granted a patent for a convolution operation method and processing device. The method involves dividing weight data into basic data blocks, distributing them to basic processing circuits, and broadcasting a portion of input data to these circuits. The operation results are then provided to the main processing circuit, which calculates the convolution operation result. This method aims to reduce operation time and energy consumption. GlobalData’s report on Cambricon Technologies gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Cambricon Technologies, User journey analytics was a key innovation area identified from patents. Cambricon Technologies's grant share as of September 2023 was 20%. Grant share is based on the ratio of number of grants to total number of patents.
Convolution operation method using parallel processing circuits
A recently granted patent (Publication Number: US11775311B2) describes a convolution operation method performed by a processing device comprising a main processing circuit and multiple basic processing circuits. The method involves receiving an input data block and a weight data block, where the input data block contains input data and the weight data block consists of convolution kernels. The weight data block is divided into basic data blocks, each containing a portion of the weight data belonging to one of the convolution kernels. These basic data blocks are then distributed to the basic processing circuits, ensuring that at least two circuits receive different basic data blocks with portions of weight data from different convolution kernels.
The main processing circuit broadcasts a portion of the input data block to all the basic processing circuits, ensuring that each circuit receives the same portion. Each basic processing circuit performs operations on the input data block and the distributed basic data blocks to obtain an operation result. These operation results are provided to the main processing circuit, which calculates the convolution operation result based on the results provided by the basic processing circuits. The method ensures that each basic data block has the same size, and the main processing circuit slides an operation window of the same size as each basic data block in the input data block. The portion of the input data block within the operation window at each sliding position is extracted and broadcasted to the basic processing circuits.
The patent also describes the arrangement of input data and weight data in four-dimensional data blocks. The input data block has dimensions for height (H), width (W), channels (C), and number of data (N). The weight data block has dimensions for kernel height (KH), kernel width (KW), channels (C), and number of data (M).
The method further explains the operations performed by the basic processing circuits, which involve multiplication operations on element values of the input data block and element values at corresponding positions of the basic data blocks. The multiplication results are accumulated to obtain a convolution result, which is then provided to the main processing circuit. The main processing circuit sorts the convolution results to obtain the final convolution operation result.
The processing device described in the patent includes a main processing circuit, basic processing circuits, and branch processing circuits for transmitting data among them. The main processing circuit can include various components such as a vector arithmetic unit circuit, an arithmetic logic unit (ALU) circuit, an accumulator circuit, a matrix transposition circuit, a direct memory access (DMA) circuit, or a data rearrangement circuit. The basic processing circuits can include inner-product arithmetic unit circuits or accumulator circuits.
Overall, this patent presents a convolution operation method and a processing device that efficiently perform convolution operations using a combination of main and basic processing circuits. The method allows for parallel processing and distribution of data, resulting in faster and more efficient convolution operations.
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