Lattice Semiconductor has been granted a patent for implementing fast boot for programmable logic devices (PLDs). The patent describes a method for programming a PLD, which involves performing read operations on different portions of a non-volatile memory to determine if a boot image is ready to be read. If ready, the PLD reads the boot image and programs the configuration memory cells based on the configuration data obtained. GlobalData’s report on Lattice Semiconductor gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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Fast boot implementation for programmable logic devices (plds)
A recently granted patent (Publication Number: US11681536B2) describes a method for programming a programmable logic device (PLD) using a non-volatile memory. The method involves several steps to ensure that the boot image stored on the non-volatile memory is ready to be read and used for programming the PLD.
Firstly, the PLD performs a read operation on a second portion of the non-volatile memory to obtain a first value. This value is then compared to a first predetermined value, which is associated with the serial flash discoverable parameters (SFDP) standard. The result of this comparison determines whether the boot image is ready to be read by the PLD.
If the boot image is not ready, the process is repeated until it is determined to be ready. Once the boot image is ready, the PLD performs a read operation on the boot image to obtain the configuration data. The PLD then proceeds to program the configuration memory cells based on this data.
The patent also describes additional features and variations of the method. For example, the first predetermined value can be stored at a predetermined address in the non-volatile memory, and the comparison result can indicate the completion status of a power sequence associated with the memory.
Furthermore, the method can be initiated during the power-on of a device that includes the non-volatile memory, and the read operation on the second portion of the memory is performed immediately after the power-on of the PLD is complete.
The patent also discusses the use of counter values and threshold values to determine the readiness of the boot image. Consecutive read operations on the second portion of the memory are used to obtain values for comparison, and the counter values are adjusted based on the comparison results.
In addition, the patent mentions the possibility of performing read operations on a third portion of the non-volatile memory and comparing the obtained value to a second predetermined value. The determination of the readiness of the boot image can be based on the comparison results from both the second and third portions of the memory.
Overall, this patent presents a method for programming a PLD using a non-volatile memory, ensuring that the boot image is ready to be read and the configuration data is accurately obtained for programming the PLD.