Samsung Electronics has been granted a patent for a non-volatile memory device featuring a vertically stacked semiconductor structure. The device includes a bypass circuit for efficient data transfer between two memory groups, enhancing data management and programming capabilities within the memory architecture. GlobalData’s report on Samsung Electronics gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Samsung Electronics, was a key innovation area identified from patents. Samsung Electronics's grant share as of July 2024 was 58%. Grant share is based on the ratio of number of grants to total number of patents.
Data transfer method in non-volatile memory device
The patent US12073888B2 outlines a method for internally transferring data within a non-volatile memory device that features a vertically stacked architecture comprising an upper semiconductor layer and a lower semiconductor layer. The upper layer contains two memory groups separated by a region, while the lower layer includes a bypass circuit. The method involves sensing data from the first memory group, storing it in the bypass circuit, and subsequently transferring it to a second memory group via a second page buffer. This process allows for the simultaneous sensing and storing of data, enhancing efficiency. The method also includes programming the data as a unitary block, which can consist of single-level or multiple-level memory cell data, and is designed to operate during idle times of the memory device.
Additionally, the patent details the role of control logic in managing the data transfer process, including generating row and column addresses for reading and programming data. The control logic activates connection control signals to facilitate the transfer of data between the bypass circuit and the page buffers. The architecture of the memory device is designed to ensure electrical isolation between the memory groups while allowing for efficient data handling through the bypass circuit. The claims also specify the arrangement of decoders and buffers in a windmill pattern within the lower semiconductor layer, further optimizing the data transfer process. Overall, the method aims to improve the performance and efficiency of data management in non-volatile memory devices.
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