Lattice Semiconductor has patented a method for fast boot in programmable logic devices (PLDs). The technique involves programming specific memory cells with configuration data to activate logic and I/O fabric functionalities in stages, allowing for quick system operation. GlobalData’s report on Lattice Semiconductor gives a 360-degree view of the company including its patenting strategy. Buy the report here.

According to GlobalData’s company profile on Lattice Semiconductor, HDMI video transmission was a key innovation area identified from patents. Lattice Semiconductor's grant share as of January 2024 was 69%. Grant share is based on the ratio of number of grants to total number of patents.

Fast boot for programmable logic devices

Source: United States Patent and Trademark Office (USPTO). Credit: Lattice Semiconductor Corp

A recently granted patent (Publication Number: US11847471B2) discloses a method for configuring a programmable logic device (PLD) efficiently. The method involves receiving configuration data associated with the PLD, programming specific memory cells with portions of the data, waking up corresponding functionalities in response to signals, and transitioning the device into a system operation mode. The process ensures the maintenance of specific functionalities within predetermined time frames, enhancing the overall operational efficiency of the PLD. Additionally, the patent details the authentication process associated with different memory cells, ensuring secure and accurate configuration of the device.

Furthermore, the patent extends to a non-transitory machine-readable storage medium containing instructions for executing the PLD configuration method. It includes operations related to fast boot functionalities, layout determination, and authentication information generation. The patent also covers the integration of these instructions into a system comprising processors, emphasizing the practical implementation of the PLD configuration process. Additionally, the patent describes a PLD itself, highlighting its array of configuration memory cells, processing circuit capabilities, and authentication procedures. The PLD's design ensures efficient programming and functionality activation, contributing to enhanced performance and reliability in various applications.

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